(1) Field of the Invention
The present invention relates generally to a method of forming a semiconductor device, and more particularly to form low resistance gate contacts in a MOSTET device.
(2) Description of the Prior Art
There has been increasing interest in the possible use of CMOS (complimentary metal-oxide-silicon) circuits for RF applications at >900 MHz, such as mobile telecommunication devices. The reasons for this are: low fabrication cost of CMOS devices compared to the currently used bipolar and GaAs integrated circuits (IC), easy integration of analog and digital components, and fundamental advantages if attainable dynamic range when a frequency mixer is required in specific applications. Furthermore, the cut-off frequency of small geometry MOSFET has become comparable to that of advanced bipolar transistors. In addition, minimum noise figure (NFmin) has also improved in the submicron devices. For these reasons, CMOS devices will be increasingly used in RF front-end IC's.
In the case of high-frequency analog MOSFET's, while high trans-conductance is important for high cut-off frequency and low noise characteristic, low gate resistance is essential for reducing thermal noise. In advanced device designs enabled by advances in process technologies, minimum feature sizes are continually decreasing. As a result, channel lengths in FET devices and thereby gate electrode widths have significantly decreased. One major problem associated with narrow gate electrode is its high electrical sheet resistance which impairs the device performance. Several methods have been proposed and used in prior art for reducing gate resistance. One method is to divide the gate electrode into several gate fingers, with each finger having provided with a contact hole, thereby increasing the total gate contact area. Another method is to use metal silicide contacts such as titanium, tungsten, or cobalt silicides or metal gates. The present invention proposes an alternate method of reducing gate contact resistance by directly contacting the gate poly-silicon with the contact metal.
U.S. Pat. No. 5,731,239 describes a method for making low sheet resistance sub-quarter micrometer gate electrode in FET devices. The method involves first patterning the gate from a doped poly-silicon layer. After forming the sidewall spacers and source/drain contact regions with Ti contacts, the insulating layer is chemically mechanically polished to the silicon nitride on the gate electrode layer. A pre-amorphizing implantation is done and a titanium silicide is selectively formed on the gate electrodes resulting in small grain sizes and reduced sheet resistance. Alternatively, cobalt silicide can also be formed on gate electrode to reduce the gate resistance.
U.S. Pat. No. 6,010,945 describes a method to form a “mushroom shaped” gate structure that increases the top gate silicide contact area and improves the salicidation process. The upper gate extensions increase the top gate surface area so that silicide gate contacts will have low resistivity.
U.S. Pat. No. 6,271,087 B1 describes a method for forming self-aligned contacts and local interconnects. Multi-layer structures are formed on a semiconductor substrate; sidewall spacers are formed around the multi-layer structures; source and drain regions are formed; a stop layer is deposited over the substrate followed by the deposition of a dielectric layer over said stop layer. A first photo-resist contact mask is used to etch core contact and peripheral local interconnect openings. After stripping the first mask, a second contact mask is formed and the multi-layer structures are etched to form local interconnect openings. After removing the second mask, a conductive film is deposited over the dielectric layer and in the core and peripheral openings, followed by chemical mechanical polishing to remove the conductive film everywhere except in the core contact and local interconnect openings.
U.S. Pat. No. 6,281,059 B1 describes a method of forming ESD protective transistor. This is done by ion implantation into the drain contact hole of the ESD protective transistor, wherein the contact hole is fabricated simultaneously with gate contact holes of the fundamental transistor and the ESD protective transistor. Both of the transistors have a respective metal silicide layer to cap the poly-silicon layer to prevent penetration of p+ ions into poly-silicon while implanting into the contact holes.